maxim integrated products 1 some revisions of this dev ice may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim - ic.com/errata . for pricing, delivery, and ordering information, please contact maxim direct at 1 - 888- 629- 4642, or visit maxim?s website at www.maxim - ic.com. ds31415 3- input, 4- output, single dpll timing ic with sub - ps output jitter and 1588 clock general description the ds31415 is a flexible, high - performance timing ic for diverse frequency conversion and frequency synthesis ap plications. on each of its three input clocks and four output clocks, the device can accept or generate nearly any frequency between 2khz and 750mhz. the input clocks are divided down, fractionally scaled as needed, and continuously monitored for activity and frequency accuracy. the best input clock is selected, manually or automatically, as the reference clock for the rest of the device. a flexible, high - performance digital pll locks to the selected reference and provides programmable bandwidth, very high resolution holdover capability , and truly hitless switching between input clocks. the digital pll is followed by a clock synthesis subsystem that has two fully programmable digital frequency synthesis blocks, a high - speed low - jitter apll, and four output clocks, each with its own 32 - bit divider and phase adjustment. the apll provides fractional scaling and output jitter less than 1ps rms . for telecom systems, the ds31415 has all required features and functions to serve as a central timing function or as a line card timing ic. in addition the ds31415 has an embedded ieee 1588 clock that can be steered by system software to follow a time master elsewhere in the system or elsewhere in the network. this clock has all necessary features to be the central time c lock in a 1588 ordinary clock, boundary clock or transparent clock. applications frequency conversion and ieee1588 time/frequency applications in a wide variety of equipment types telecom line cards or timing cards with any mix of sonet/sdh, synchronous e thernet and/or otn ports in wan equipment including mspps, ethernet switches, routers, dslams, and base stations ordering information part temp range pin - package ds31415 gn+ - 40 c to +85 c 256 csbga + denotes a lead (pb) - free/rohs - compliant package. spi is a trademark of motorola, inc. features ? three input clocks ? differential or cmos/ttl format ? any frequency from 2khz to 750mhz ? fractional scaling for 64b/66b and fec scaling (e.g. , 64/66, 237/255, 238/255) or any other downscaling requirement ? continuous inpu t clock quality monitoring ? three 2/4/8khz frame sync inputs ? high - performance dpll ? hitless reference switching on loss of input ? automatic or manual phase build - out ? holdover on loss of all inputs ? programmable bandwidth, 0.5m hz to 400hz ? two digital frequency synthesizers ? produce any 2 khz multiple u p to 77.76mhz ? per - dfs phase adjust ment ? high - performance output apll ? output frequencies to 750 mhz ? high resolution fractional scaling for fec and 64b/66b (e.g. , 255/237, 255/238, 66/64) or any other scaling requiremen t ? less than 1ps rms output jitter ? four output clocks in two groups ? nearly any frequency from < 1hz to 750mhz each group slave s to a dfs clock, any apll clock, or any input clock (divided and scaled) ? each has a differential output (3 cml, 4 lvds/ lvpecl ) a nd separate cmos/ttl output ? 32- bit frequency divider per output ? two sync pulse outputs: 8khz and 2khz ? ieee 1588 clock features ? steerable by software with 2 - 8 ns time resolution and 2 - 32 ns frequency resolution ? 4ns input timestamp accuracy and output edge pl acement accuracy ? programmable clock and time - alignment i/o to synchronize all 1588 devices in large s ystems ? supports 1588 oc, bc , and tc a rchitectures ? general features ? suitable line card ic or timing card ic for stratum 2/ 3 e/3/ 4 e/4, smc, sec/eec , or ssu ? ac cepts and produces nearly any frequency from 1hz u p to 750mhz ? internal compensation for local oscillator frequency error ? spi? processor interface ? 1.8v operation with 3.3v i/o (5v tolerant) 19 - 5712; rev 2 ; 7 /11 abridged data she et
ds31415 2 application example typical application example , traditional freq uency synchronization recovered line clocks from system backplane, sdh, synce, otn, etc. ic1 ds31415 ic2 19.44mhz, 38.88mhz, 25mhz, etc. system clocks to line cards outputs from apll: <1ps rms jitter, outputs from dfs: ~40ps rms jitter clock monitoring and selection, hitless switching, holdover, phase build-out, frequency conversion, fractional scaling, jitter attenuation oc1 oc2 oc1pos/neg this diagram is just one example. many other applications are possible. 19.44mhz, 38.88mhz, 25mhz, etc. oc2pos/neg mfsync time alignment signal to line cards (e.g. 1 pps) typical application example , frequency and time synchronization system time, e.g. 1 pps to all port cards line clocks, e.g. 25mhz from port cards, for synce or 1588+synce operation ds31415 spi local osc tcxo or ocxo system clock, e.g. 25mhz other clocks processor 1588 software packet data to/from central switch function dpll 1588 clock abridged data sheet
ds31415 3 block diagram dpll filtering, holdover, hitless switching, pbo, frequency conversion, manual phase adjust microprocessor port (spi or i2c serial) and hw control and status pins rst cs cpha sclk sdi sdo intreq srcsw jtag sync1 test gpio[4:1] srfail lock sync3 ic1 pos/neg ic2 pos/neg sync2 oc1pos/neg oc4 cpol jtrst jtms jtclk jtdi jtdo divider 4 oc1 ds31415 lowest jitter path pll bypass oc4pos/neg ic3 pos/neg divider 1 divider muxes dif mux input clock block frequency scaler, activity monitor, freq. monitor, optional inversion (per input clock) clock selector 3 status clkin 1588 clock tain syncx out1 out2 icx ocx icx ocx to divider muxes mclk master clock apll local oscillator tcxo or ocxo mclkosc oscfreq[2:0 ] fsync mfsync 1588 out1 mfsync 1588 out2 dfs 1 apll1 dfs 4 dfs muxes abridged data sheet
ds31415 4 detailed features input clock features ? three input clocks, differential or cmos/ttl signal format ? input clocks can be any frequency from 2khz up to 750mhz ? per - input fractional scaling (i.e. , multiplying by n d where n is a 16 - bit integer and d is a 32- bit integer and n < d ) to undo 64b/66b and fec scaling (e.g. , 64/66, 238/255, 237/255, 236/255) ? special mode allows locking to 1hz input clocks ? all inputs constantly monitored by programmable activity monitors and frequency monitors ? fast activity monitor can disqualify the selected reference after a few missing clock cycles ? frequency measurement and freque ncy monitor thresholds with 0.2 ppm resolution ? three optional 2/4/8khz frame - sync inputs dpll features ? very high - resolution dpll architecture ? sophisticated state machine automatically transitions between free - run, locked, and holdover states ? revertive or nonrevertive reference selection algorithm ? progr ammable bandwidth from 0.5m hz to 400hz ? separately configurable acquisition bandwidth and locked bandwidth ? programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10 , or 20 ? multiple phase detectors: phase/frequency and multicycle ? phase/ frequency locking ( 360 capture) or nearest edge phase locking ( 180 capture) ? multicycle phase detection and locking (up to 8191ui) improves jitter tolerance and lock time ? phase build - out in response to reference switching for true hitless switching ? les s than 1 ns output clock phase transient during phase build -out ? output phase adjustment up to 200ns in 6ps steps with respect to selected input reference ? high - resolution frequency and phase measurement ? holdover frequency averaging over 1 - second, 5.8- minute , and 93.2 - minute intervals ? fast detection of input clock failure and transition to holdover mode ? low - jitter frame sync (8khz) and multiframe sync (2khz) aligned with output clocks digital frequency synthesizer features ? two indepen dently programmable dfs engines ? each dfs can synthesize any 2kh z multiple up to 77.76mhz ? per - dfs phase adjust (1/256ui steps) ? approximately 4 0ps rms output jitter output apll features ? simultaneously produce four different output frequencies from the same reference clock ? standard telecom output frequencies include 622.08mhz, 155.52mhz , and 19.44mhz for sonet/sdh and 156.25mhz, 125mhz , and 25mhz for synchronous ethernet ? very high - resolution fractional scaling (i.e. , noninteger multiplication) ? less than 1 ps rms output jitter abridged data sheet
ds31415 5 output clock features ? four output clock signals in two groups ? output clock group oc1 has a very high - speed differential output (current - mode logic, 750 mhz) and a separate cmos/ttl output ( 125 mhz) ? output clock group oc4 has a high - speed differential output (l vds/lvpecl, 312.5 mhz) and a separate cmos/ttl output ( 125mhz ) ? each output can be any frequency from < 1hz to max frequency stated above ? supported telecom frequencies include pdh, sdh, synchronous ethernet, otn, microprocessor clock frequencies , and muc h more ? internal clock muxing allows each ou tput group to slave to its associated dfs block, an apll output , or any input clock (after being divided and scaled) ? outputs sourced directly from the apll have less than 1 ps rms output jitter ? outputs sourced dire ctly f rom dfs engines have approximately 4 0ps rms output jitter ? optional 32 - bit frequency divider per output ? 8khz frame sync and 2khz multiframe sync outputs have programmable p olarity and pulse width and can be disciplined by a 2khz or 8khz frame sync in put ? per - output delay adjustment ? per - output enable/disable ? all outputs disabled during reset 1588 clock features ? initialized and steered by software on an external processor to follow an external 1588 master ? 2 -8 ns time resolution and 2 - 32 ns frequency reso lution ? 4ns accuracy for input signal timestamping and output signal edge placement ? three time/frequency controls: direct time write, high - resolution frequency adjustment, and time adjustment (i.e. , frequency adjustment for an exact duration to achieve grad ual, precise time change) ? programmable clock and time - alignment i/o to synchronize all 1588 elements in large systems o can frequency - lock to an input clock signal from a master elsewhere in the system o can timestamp (ts) an input alignment signal to time - loc k to a master elsewhere in the system (e.g. , 1pps) o can provide an output clock signal to slave components elsewhere in the system (e.g. , 25mhz) o can provide an output time alignment signal to slaves elsewhere in the system (e.g. , 1pps) ? two flexible programm able event generators (peg) can output one pulse per second (1pps), one pulse per period, and a wide variety of clock signals ? full support for dual redundant timing cards for high - reliability, fault - tolerant systems ? compatible with a wide variety of 1588 s ystem architectures for 1588 ordinary clocks, boundary clocks and transparent clocks general features ? spi serial microprocessor interface ? four general - purpose i/o pins ? register set can be write protected ? operates from a 12.8mhz, 25.6mhz, 10.24mhz, 20.48mhz , 10mhz, 20mhz, 19.44mhz , or 38.88mhz local oscillator ? on - chip watchdog circuit for the local oscillator ? internal compensation for local oscillator frequency error note to readers: this document is an abridged version of the full data sheet. to request t he full data sheet, go to www.maxim - ic.com/ds31415 and click on request full data sheet . abridged data sheet
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